TL880 Register Map - Incomplete

Written 2003, Mike Bourgeous

No warranty on accuracy or fitness for any purpose is made of this data.
This data may be freely redistributed or referenced in the creation of
any work, as long as credit is given to those who took the time to create it.

Be aware that this document will not stay current. For the latest information,
see the tl880doc.txt file in the doc/ directory of the TL880 Linux Driver source
distribution. Really this should all be put in a simple database allowing the
automatic generation of human-readable versions in text and HTML, easy
editing of existing entries, automatic sorting of new entries, quick changes
to formatting, and search functionality.

All numbers are in hexadecimal, except for bit descriptions (binary).

Index:

HIF 0-14
VSC 1000-1028
APU 3000-307c
BLT 4000-405c
PLL 5000, 5400, 5800
MCE 6000-603c
VPIP 7000-7030
HPIP 8000-8024
DPC 10000-101fc

DPC2 10180-10184
GPIO 10190-1019c

MCU 18000-1fffc
TSD 20000-27ffc
MIF 28000-280dc

Section	Register	Description
HIF 0-14	0	Last queued TL880 interrupt bitfield
	4	Interrupt enable mask
		Registers 0-4: Known interrupt types are in tl880kern.c: tl880_bh(). If a demux interrupt is received (interrupt type \| 0x400), it is important to clear that bit in the interrupt enable mask before leaving the interrupt handler, and only reset the bit when the TSD has been dealt with; otherwise, it will continually interrupt the processor, preventing anything else from happening. Without any data fed to the TSD, reading from register 27814 after the first TSD interrupt will cause it to stop interrupting. A similar warning applies to any other type of interrupt.
	8	Possibly last queued interrupt from c
	c	Possibly an interrupt enable mask
VSC 1000-1028	1000	Used in SetVSCCtrl Bit 0 set to 1 in EnableVSC Used in VBICaptureStream::OnSetState 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 VSC Enable (?) 0 in cJanus::StartNtsc->SetVSCCtrl 00000000\|00000000\|00000000\|00000010 0 in cJanus::StartNtsc->SetVSCCtrl 00000000\|00000000\|00000000\|00000100 0 in cJanus::StartNtsc->SetVSCCtrl 00000000\|00000000\|00000000\|00001000 0 in cJanus::StartNtsc->SetVSCCtrl 00000000\|00000000\|00000000\|00010000 1 in cJanus::StartNtsc->SetVSCCtrl 00000000\|00000000\|00000000\|00100000 0 in cJanus::StartNtsc->SetVSCCtrl 00000000\|00nnnnnn\|nnnnnnnn\|nn000000 0x64 in cJanus::StartNtsc->SetVSCCtrl
	1008	VSC interrupt enable mask
	100c	Last queued VSC interrupt bitfield
	1010	Used in cJanus::RotateVscCapFrame (bits 0xb-0x8,0x3-0x0) Used in SetVSCMIF SetVSCMIF writes the register and then verifies with ReadTL850RegBits up to 5 times `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|0000nnnn 0 in cJanus::StartNtsc->SetVSCMIF 00000000\|00000000\|0000nnnn\|00000000 1 in cJanus::StartNtsc->SetVSCMIF`
	1014	Written with 0x61777 in cJanus::StartNtsc Used in SetVSCScaler `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|0000nnnn\|nnnnnnnn\|nnnnnnnn (arg4 << 13) / arg0 in SetVSCScaler (arg0=arg4=720 in cJanus::StartNtsc->SetVSCScaler) nnnnnnnn\|00000000\|00000000\|00000000 0 in SetVSCScaler`
	1018	Written with 0x2d002d0 in cJanus::StartNtsc Used in SetVSCScaler `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|000000nn\|nnnnnnnn arg0 in SetVSCScaler 000000nn\|nnnnnnnn\|00000000\|00000000 arg4 in SetVSCScaler`
	101c	Used in SetVSCVBI `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|000000nn\|nnnnnnnn arg0 in SetVSCVBI 0000000n\|nnnnnnnn\|00000000\|00000000 arg4 in SetVSCVBI`
	1020	Used in SetVSCVBI `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|000000nn\|nnnnnnnn arg8 in SetVSCVBI 0000000n\|nnnnnnnn\|00000000\|00000000 argc in SetVSCVBI`
	1024	Used in SetVSCVBI `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 000000nn\|nnnnnnnn\|nnnnnnnn\|nnnnn000 arg10 in SetVSCVBI`
	1028	Used in SetVSCVBI `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 000000nn\|nnnnnnnn\|nnnnnnnn\|nnnnn000 arg10 in SetVSCVBI`
APU 3000-307c	3000	Used in cJanus::InitNtscAudio Set to zero in cJanus::DisableAPU 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 0 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|00000010 0 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|00000100 0 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|000nn000 0 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|0nn00000 0 in cJanus::InitNtscAudio 00000000\|00000000\|0000000n\|n0000000 0 in cJanus::InitNtscAudio 00000000\|00000000\|00000nn0\|00000000 0 in cJanus::InitNtscAudio 00000000\|00000000\|10000000\|00000000 0 in cJanus::InitNtscAudio 00000000\|000000nn\|00000000\|00000000 !gMspI2sMaster in cJanus::InitNtscAudio 00000000\|0000nn00\|00000000\|00000000 !gMspI2sMaster in cJanus::InitNtscAudio 00000000\|00nn0000\|00000000\|00000000 0 in cJanus::InitNtscAudio 00000000\|nn000000\|00000000\|00000000 0 in cJanus::InitNtscAudio 000000nn\|00000000\|00000000\|00000000 1 in cJanus::InitNtscAudio
	3004	Bit 2 -- stereo/mono NTSC audio Set to zero in cJanus::InitNtscAudio Set to zero in cJanus::DisableAPU `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 1 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|0nnnnnn0 3 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|10000000 1 in cJanus::InitNtscAudio 00000000\|00000000\|00000001\|00000000 1 in cJanus::InitNtscAudio 00000000\|00000000\|00000nn0\|00000000 1 in cJanus::InitNtscAudio`
	3008	Used in cJanus::InitNtscAudio `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 1 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|000nn000 1 in cJanus::InitNtscAudio 00000000\|00000000\|00000000\|0nn00000 1 in cJanus::InitNtscAudio 00000000\|00000000\|00000nnn\|00000000 0 in cJanus::InitNtscAudio 00000000\|00000000\|0nnn0000\|00000000 1 in cJanus::InitNtscAudio`
	300c	Written with 0x3000000
	3010	Written with 0x3000000
	3014	APU interrupt enable mask
	3018	Last queued APU interrupt bitfield
	3020	Written with 0x1000 in cJanus::InitNtscAudio Used in cJanus::NtscAudioDpc
	3024	Written with 0x10fe0 in cJanus::InitNtscAudio Used in cJanus::NtscAudioDpc
	3028	May be NTSC recording offset in SDRAM Used in cJanus::RotateVscCapFrame Used in cJanus::InitNtscAudio (0x1000 + gpJanus[167d8] myhd1.54)
	302c	Written with 0x1000 in cJanus::InitNtscAudio
	3030	Written with 0x9000 in cJanus::InitNtscAudio Used in cJanus::NtscAudioDpc
	3034	APU_IAU_IBA_REG - written with _IAU_BASE
	3038	APU_IAU_IRA_REG - written with _IAU_BASE + 0x77fc
	303c	APU_IAU_IEA_REG - written with _IAU_BASE
		_IAU_BASE is 0x7800 bytes memory allocated with yGetTL850Memory
	305c	Written with 0xc30000c3 in cJanus::InitNtscAudio
	3060	Written with 0x0 in cJanus::InitNtscAudio
	3064
	3068
	306c	Written with 0xc30000c3 in cJanus::InitNtscAudio
	3070	Written with 0x0 in cJanus::InitNtscAudio
	3074
	3078
	307c	Written with 0xc30000c3 in cJanus::InitNtscAudio
BLT 4000-405c	4010	BLT interrupt enable mask
BLT 4000-405c	4014	Last queued BLT interrupt bitfield
	5000	SysPllEq
	5400	MifPllEq
	5800	DPC PLL constant 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000xxx Disable sync if set(?) 00000000\|00000000\|00000000\|00001000 Divide by two? 00000000\|00000000\|00000000\|00nn0000 c - 0: off/double, 1/2: on, 3: half speed 00000000\|00000000\|000nnnnn\|00000000 b - 0: normal, 2: half, 6: quarter e: eighth, 1e: sixteenth (sometimes) 000000nn\|nnnnnnnn\|00000000\|00000000 a: base
MCE 6000-603c	6000	Used in cJanus::GetTocRdPtr, cJanus::ResetMce, cJanus::UpdateMce, cJanus::InitMce Bit 0 written with 1 in cJanus::InitMceToc Bits 0xa-0x9 and 0x8-0x8 written with write_regbits in UpdateMce Written with 0xc000 (bits 0xe, 0xf) in cJanus::InitMce
	6004	Used in cJanus::GetTocRdPtr, cJanus::ResetMce, cJanus::UpdateMce, cJanus::InitMce
	6008	MCE interrupt enable mask
	600c	Last queued MCE interrupt bitfield
	6014	Used in isr_StartCodeSearch, cJanus::SearchHdrWithPacing Written with 3 in cJanus::isr_NonSlice_Tv
	6018	Used in cJanus::SearchHdrWithPacing as a bitfield
	6024	Used in InitVldShiftAmt Bits 0x4-0x0 written with 0 in cJanus::InitMceToc
	602c	Used in LoadQuantTable; write 0x400 then table values?
	6030	Written with values or'd together 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 tagContext[0xec] 00000000\|00000000\|00000000\|00000010 tagContext[0xe8] 00000000\|00000000\|00000000\|00000100 tagContext[0xe4] 00000000\|00000000\|00000000\|00001000 tagContext[0xdc] 00000000\|00000000\|00000000\|00nn0000 tagContext[0xd0] 00000000\|00000000\|00000000\|nn000000 tagContext[0xd4] 00000000\|00000000\|00000nnn\|00000000 tagContext[0x94] 00000000\|00000000\|nnnnn000\|00000000 tagContext[0xe0] 00000000\|0000nnnn\|00000000\|00000000 tagContext[0xcc] 00000000\|nnnn0000\|00000000\|00000000 tagContext[0xc8] 0000nnnn\|00000000\|00000000\|00000000 tagContext[0xc4] nnnn0000\|00000000\|00000000\|00000000 tagContext[0xc0]
	6034	Used in cJanus::GetTocRdPtr, cJanus::ResetMce, cJanus::InitMceToc
	6038	Used in cJanus::ResetMce, cJanus::InitMceToc
	603c	Used in cJanus::ChannelChangeStep2, cJanus::InitMceToc
VPIP 7000-7030	7000	Used in cJanus::VpipSetting, cJanus::StartVpip 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|000000nn 00000000\|00000000\|00000000\|0000nn00 00000000\|00000000\|00000000\|00010000 1 in cJanus::VpipSetting 00000000\|00000000\|00000000\|00100000 0 in cJanus::VpipSetting 00000000\|00000000\|00000000\|01000000 0 in cJanus::VpipSetting 00000000\|00000000\|00000000\|10000000 0 in cJanus::VpipSetting 00000000\|00000000\|0000nnnn\|00000000 3 in cJanus::VpipSetting 00000000\|00000000\|00nn0000\|00000000 00000000\|00000000\|01000000\|00000000 1 or 0 in cJanus::VpipSetting 00000000\|00000000\|01000000\|00000000 1 or 0 in cJanus::VpipSetting 00000000\|00nnnnnn\|00000000\|00000000 3f in cJanus::VpipSetting, cJanus[10f94][d8] in cJanus::StartVpip 00000000\|01000000\|00000000\|00000000 0 in cJanus::VpipSetting (field order?)
	7004	VPIP interrupt enable mask Bit zero set to 1 in cJanus::VpipSetting
	7008	Last queued VPIP interrupt bitfield
	700c	Used in cJanus::DeinterlaceTop, cJanus::NtscDpcEofService, cJanus::VpipSetting, cJanus::UpdateVpipBufReg, cJanus::DeinterlaceBottom 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|0000nnnn tagContext[1d4] in cJanus::DeinterlaceTop tagContext[1d4] in cJanus::DeinterlaceBottom 00000000\|00000000\|0000nnnn\|00000000 tagContext[368] in cJanus::DeinterlaceTop tagContext[1d8] in cJanus::DeinterlaceBottom 00000000\|0000nnnn\|00000000\|00000000 tagContext[1bc] in cJanus::DeinterlaceTop tagContext[1c4] in cJanus::DeinterlaceBottom 0000nnnn\|00000000\|00000000\|00000000 tagContext[1c0] in cJanus::DeinterlaceTop tagContext[1c8] in cJanus::DeinterlaceBottom
	7010	Used in cJanus::VpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|0000nnnn\|nnnnn000 0 in cJanus::VpipSetting 0000nnnn\|nnnnn000\|00000000\|00000000 0 in cJanus::VpipSetting`
	7018	Used in cJanus::VpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|0000nnnn\|nnnn0000`
	701c	Used in cJanus::StartVpip (Written with cJanus[10f94][10])
	7020	Used in cJanus::VpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|000000nn\|nnnnnnnn Vertical scaling ratio (1080/540 or /720)? 00000000\|000nnnnn\|nnnnnn00\|00000000 nnnnnnnn\|nnn00000\|00000000\|00000000`
	7024	Passed to cJanus::LoadFilterCoeffs in cJanus::VpipSetting
	7028	Passed to cJanus::LoadFilterCoeffs in cJanus::VpipSetting
	702c	Used in cJanus::StartVpip(2) Always seems to be written first or'd with 0x80000000 (bit 0x1f), then without `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|0nnnnnnn\|nnnn0000\|00000000 10000000\|00000000\|00000000\|00000000`
HPIP 8000-8024	8000	Used in cJanus::HpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 HPIP enable 00000000\|00000000\|00000000\|00000010 0 in cJanus::HpipSetting 00000000\|00000000\|00000000\|00000100 0 in cJanus::HpipSetting`
	8008	HPIP interrupt enable mask
	800c	Last queued HPIP interrupt bitfield
	8010	HpipBufReg(?) Used in cJanus::HpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|0000nnnn tagContext[0x1a4] 00000000\|00000000\|000nnnnn\|00000000 tagContext[0x1a8]`
	8014	Used in cJanus::HpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|0nnnnnnn tagContext[0x254]/16 00000000\|00000000\|0nnnnnnn\|00000000 00000000\|0nnnnnnn\|00000000\|00000000 0nnnnnnn\|00000000\|00000000\|00000000`
	8018	Used in cJanus::HpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|0nnnnnnn tagContext[0x254]+15/16 or +31/32`
	801c	Used in cJanus::HpipSetting `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|000000nn\|nnnnnnnn 00000000\|000nnnnn\|nnnnnn00\|00000000 nnnnnnnn\|nnn00000\|00000000\|00000000`
	8020	Passed to cJanus::LoadFilterCoeffs in cJanus::HpipSetting
	8024	Passed to cJanus::LoadFilterCoeffs in cJanus::HpipSetting
DPC 10000-101fc	10000	Display options bitfield 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 Top/bottom field or top/bottom buffer 00000000\|00000000\|00000000\|00000010 Image display enable (BVDO) 00000000\|00000000\|00000000\|00000100 OSD display enable 00000000\|00000000\|00000000\|00001000 Cursor display enable(?) 00000000\|00000000\|00000000\|00010000 Aux (i.e. video card overlay) enable 00000000\|00000000\|00000000\|00100000 Sync enable/external display enable (not sure) 00000000\|00000000\|00000000\|01000000 This does something to the color. 00000000\|00000000\|00000001\|00000000 Color bars 00000000\|00000000\|00000100\|00000000 Y'PbPr color (needs other settings too)
	10004	Status register for the video generator (?) Used in isr_VideoSync_Tv Probably read-only (never reflects writes) `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000100 Read in isr_VideoSync_Tv`
	10008	DPC interrupt enable mask `00000100 isr_VideoSync (vertical retrace?) 00100000 IntDpcEof0 (end of top field?) 01000000 IntDpcEof1 (end of bottom field?) bit 9 may be preview client/aux video? bit 0xa may be capture client/aux video?`
	1000c	Last queued DPC interrupt bitfield
	10014	DPC sync register 1 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000001 A 00000000\|00000000\|00000000\|00000010 B 00000000\|00000000\|00000000\|00000100 C 00000000\|00000000\|00000000\|00001000 D - Progressive Scan 00000000\|00000000\|nnnnnnnn\|nn000000 E 00000nnn\|nnnnnnnn\|00000000\|00000000 F - Horizontal Size 00001000\|00000000\|00000000\|00000000 G 00010000\|00000000\|00000000\|00000000 H 00100000\|00000000\|00000000\|00000000 I 01000000\|00000000\|00000000\|00000000 J
	10018	DPC sync register 2 - Horizontal scan parameters, sync polarity `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|0000000n\|nnnnnnnn K - Horizontal Back Porch 00000000\|00000000\|00000010\|00000000 L - Invert Hsync 00000000\|00000000\|00000100\|00000000 M - Invert Vsync 00000000\|00000nnn\|nnnn0000\|00000000 N - Horizontal Sync Length 000nnnnn\|nnnn0000\|00000000\|00000000 O - Horizontal Front Porch`
	1001c	DPC sync register 3 - First/only field vertical scan parameters `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000nnn P - Vertical Sync Length 1 00000000\|00000000\|0000nnnn\|nnnn0000 Q - Vertical Front Porch 1 00000000\|0nnnnnnn\|nnnn0000\|00000000 R - Vertical Size 1 0000nnnn\|00000000\|00000000\|00000000 S - Vertical Back Porch 1 00010000\|00000000\|00000000\|00000000 T`
	10020	DPC sync register 4 - Second field vertical scan parameters `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|00000nnn U - Vertical Sync Length 2 00000000\|00000000\|0000nnnn\|nnnn0000 V - Vertical Front Porch 2 00000000\|0nnnnnnn\|nnnn0000\|00000000 W - Vertical Size 2 0000nnnn\|00000000\|00000000\|00000000 X - Vertical Back Porch 2`
	10024	DPC sync register 6 `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00nnnnnn\|nnnnnnnn\|nnnnnnnn Y 00000001\|00000000\|00000000\|00000000 Z nnnn0000\|00000000\|00000000\|00000000 AA`
	10028	DPC sync register 5 `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|0000nnnn\|nnnnnnnn BB 00000001\|00000000\|00000000\|00000000 CC`
		Register 5800 is `DD`. Letters correspond to columns in the TL880 Mode List.
	10040	Bottom two bits used in DoProgressiveFrame as a bitfield, apparently some kind of register selection for 10068, 1006c Used in cJanus::isr_NonSlice_Tv `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|000000nn 00000000\|00000000\|00000000\|00100000 1 in cJanus::isr_NonSlice_Tv`
	10048	DispBufReg(?) or NtscDispFrame? Bits 0x1e-0x14,0x11-0x8,0x7-0x4,0x3-0x0 used in cJanus::RotateNtscDispFrame
	10068	Used in DoProgressiveFrame with g_vsCtlReg
	1006c	Used in DoProgressiveFrame with g_vsCtlReg
	10070	Used at end of DoProgressiveFrame
		Registers 10080 to 100ac are the OSD context
	10080	Seems to be a TL880 memory offset - changes palettes(?)
	10084	Seems to be a TL880 memory offset - changes OSD image(?) Something like "sdram offset" - used in overlay display lists
	10094	Used in showOverlays `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|nnnnnnnn\|00000000 0x80 in showOverlays`
	100c0	Used in auxSetVertScaler Bit 2: used in JanusProperty::SetProperty near a reference to g_auxCompVideo Bit 5: CDma::DisableDmaHW (set to 0), CDma::DmaRelatedHWSettings (set to 1)
	100c4	Used in auxSetPictureOrigin
	100c8	Used in auxSetHrzScaler
	100cc	Used in auxSetVertScaler
	100d0	Used in auxSetHrzScaler
	100d4	Used in auxSetVertScaler
	100d8	Used in auxSetVertScaler
	10100	Used in showCursor `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 000000nn\|nnnnnnnn\|nnnnnnnn\|nnnn0000`
	10104	Used in setCursorPosition `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000nnn\|nnnnnnnn Axis 1 (X?) 00000nnn\|nnnnnnnn\|00000000\|00000000 Axis 2 (Y?)`
	10108	Used in showCursor `11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000000\|nnnnnnnn 00000000\|nnnnnnnn\|00000000\|00000000 000000nn\|00000000\|00000000\|00000000`
	10140 ⋅ ⋅ 10180	Written with Y'PbPr values in OSDProperty::SetProperty
	10180	DPC2: 10180 and 10184 do some weird stuff.. 10180 seems to possibly be a register select/status, and 10184 is register/status content.
	10184
	GPIO 10190-1019c	General Purpose Input/Output pins on the TL880 chip
	10190	GPIO enable
	10194	GPIO output enable (I/O direction)
	10198	GPIO output I²C output Used in cNxtVSB::NxtCheckChannel
	1019c	GPIO input I²C input
		`MyHD: to turn on external display: register sync value dump value -------- ---------- ---------- 10190 0x00000400 0x0cffffff 10194 0x00000400 0x000eff00 10198 0x00000400 0x000e5d00` MyHD MDP-110 GPIO ----------------- 11111111\|11111111\|00000000\|00000000 fedcba98\|76543210\|fedcba98\|76543210 --------+--------+--------+-------- 00000000\|00000000\|00000100\|00000000 Video passthrough 00000000\|00000001\|00000000\|00000000 SDA Read 1 00000000\|00000010\|00000000\|00000000 SDA Write 1 00000000\|00000100\|00000000\|00000000 SCL Write 1, SCL Read 1 00000000\|00001000\|00000000\|00000000 cNxtVsb::NxtCheckChannel 00000000\|01000000\|00000000\|00000000 SDA Write 2, SDA Read 2 00000000\|10000000\|00000000\|00000000 SCL Write 2, SCL Read 2 00000100\|00000000\|00000000\|00000000 SCL Write 0, SCL Read 0 00001000\|00000000\|00000000\|00000000 SDA Write 0, SDA Read 0 GPIO also controls sampling clock
	101a0	Zeros for bi-level (VGA) sync, something else for tri-level sync
	101a4
	101a8
MCU 18000-1fffc	18000	MCU firmware start (Length usually (always?) 0x72a registers) MCU instructions are two bytes wide; one instruction is written to each four byte register.
	1c000	MCU data start (Length always 0x200 registers) MCU data is in two byte words; one word is written to each four byte register.
	1c2c0	Used in UpdateMce
	1c2c4
	1c2c8
	1c2cc
	1c2d4 ⋅ ⋅ 1c2ec	Used in UpdateMce
	1c2f0	Bit zero - startmcu Set to zero in firmware upload
	1c2f4	MCU interrupt enable mask
	1c2fc	Used in UpdateMce
	1c300	Used in UpdateMce
	1c304	Interrupt enable mask of some type (?)
	1d800	Used in cJanus::RestartMce, cJanus::UpdateMce, cJanus::ResetMcu Set to 5 before firmware upload, 6 after firmware upload
	1d804	Used in cJanus::RestartMce, cJanus::UpdateMce, cJanus::ResetMcu Set to zero in firmware upload
	1d810	MCU status (?)
TSD 20000-27ffc	20000	TSD firmware start (Length varies from card to card) MyHD Length 0x701 (1.55.3.9e) WinTV-HD Length 0x600 (2120114)
	24000 ⋅ ⋅ 257fc	Used in demux_init
	24040	Used in Demux_tsdStart/Stop
	24048	Interrupt enable mask of some type, maybe TSD (?)
	24060 ⋅ ⋅ 24078	Used in Demux_UpdatePCR
	240a4	Used in Demux_commandTableWrite
	247e8	247e8 plus some offset is used in SetChannelWritePtr
	24be8	24be8 plus some offset is used in SetPesChannelWritePtr
	24d68	24d68.. used in InitPSI
	25718 ⋅ ⋅ 25724	Used in _auxLdDscMbox (called in VopLoadDescriptor)
	25728	Used in _auxLdDscMbox (called in VopLoadDescriptor) Used in _auxTstDscrMboxEmpty
	2573c	Used in _auxTstCurLineCnt
	25740	Used in _auxEnable/DisableDscInt, may be an interrupt mask
	25744	Used in auxSetAuxReset
	25750	Used in _auxLdDscMbox (called in VopLoadDescriptor)
	25754	Used in _auxLdDscMbox (called in VopLoadDescriptor)
	25768 ⋅ ⋅ 257e8	Demux command table?
	26800	Used in Demux_stop and demux_init
	26804	Used in Demux_stop and demux_init
	27804	Used in Demux_GetSTC (([27804] >> 0xf) \| ([27808] << 0x11)) Probably read-only
	27808
	27810	Written with _setValue in Demux_UpdatePCR Written with 0xa000 in cJanus::SetNtscAudioClock
	27814	Last queued TSD interrupt bitfield
MIF 28000-280dc	28040 ⋅ ⋅ 2807c	Used in cJanus::PipMifBufSetting
MIF 28000-280dc	280dc	Written with 0x31415926 in cJanus::RestartMce
Some of the values sometimes written to a few registers: 00000004 0000009B 00001010 00000100 00001010 00000102 00001010 00000302 00001010 00000304 00001010 00000504 00001010 00000506 00001010 00000700 00001010 00000706 00007000 00000015 00007000 007DE310 0000700C 09080700 0000701C 00000090 0000701C 00000092 0000701C 03E07C90 0000701C 03E07C92 0000701C 07C0F892 0000701C 0F81F090 0000701C 0F81F092 0000702C 00000000 0000702C 80000000 00010000 00000032 00010000 00000033 00010048 00C00098 00010048 00C000BA 00025718 00001F54 0002571C 0000A280 00025720 0000A000 00025724 0000A000 00025728 0000000C 00025758 0000FF14 The OSD addresses all get OR'd with 0x52300000.